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podświetlone jako vhdl (dodał(a) VHDL Master @ 2009-02-01 03:21:03)

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--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  TEST_STATE
--* Filename & Ext  :  test_state.vhdl
--* Author          :  David W. Bishop
--* Created         :  Apr 19, 1996 
--* Version         :  1.2
--* Revision Date   :  97/02/17
--* SCCSid          :  1.2 2/17/97 test_state.vhdl
--* WORK Library    :  chiptest
--* Mod History     :  
--* Description     :  This is an example state machine for VHDL.
--* Known Bugs      :  
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
library ieee;
use ieee.std_logic_1164.all;
 
entity test_state is
  port ( clk              : in  std_ulogic;
         reset            : in  std_ulogic;
         con1, con2, con3 : in  std_ulogic;
         out1, out2       : out std_ulogic );
end test_state;
 
-------------------------------------------------------------------------------
--  Example of a MOORE machine (outputs come from CASE statment)
--  Note that with this type of state machine you must specify the state
--  of ALL of the outputs of your state machine.  Otherwise, you get
--  latches.
-------------------------------------------------------------------------------
 
architecture rtl of test_state is
  type   state_type is (s0, s1, s2, s3);
  signal state, next_state : state_type;
begin  --  rtl 
 
  state_encode : process ( state, con1, con2, con3 )
  begin
    next_state <= s1;  -- Note:  This line will optomize your state machine
    -- in synthesis.  It does nothing in simulation.
    case state is
      when s0 =>
        next_state <= s1;
      when s1 =>
        if ( con1 = '1' ) then
          next_state <= s2;
        else
          next_state <= s1;
        end if;
      when s2 =>
        next_state <= s3;
      when s3 =>
        if ( con2 = '0' ) then
          next_state <= s3;
        elsif ( con3 = '0' ) then
          next_state <= s2;
        else
          next_state <= s0;
        end if;
    end case;
  end process state_encode;
 
  state_register : process ( reset, clk )
  begin
    if ( reset = '0' ) then
      state <= s0;
    elsif ( clk'event and clk = '1' ) then
      state <= next_state;
    end if;
  end process state_register;
 
  state_decode : process ( state, con1, con2, con3 )
  begin
    case state is
      when s0 =>
        out1 <= '0';
        out2 <= '0';
      when s1 =>
        out1 <= '1';
        out2 <= '0';
      when s2 =>
        out1 <= '0';
        out2 <= '1';
      when s3 =>
        if ( con2 = '0' ) then
          out1 <= '0';
          out2 <= '0';
        elsif ( con3 = '0' ) then
          out1 <= '0';
          out2 <= '1';
        else
          out1 <= '1';
          out2 <= '1';
        end if;
    end case;
  end process state_decode;
 
end rtl;
 
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